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Ordering number : EN5003
CMOS LSI
LC66556B, 66558B
Four-Bit Single-Chip Microcontrollers with 6 k and 8 k Bytes of On-Chip ROM
Overview
The LC66556B and LC66558B are four-bit single-chip CMOS microcontrollers that integrate on a single chip all the functions required in a microcontroller, including ROM, RAM, I/O ports, two serial interfaces, comparator inputs, three-value inputs, timers and interrupts. These products are provided in a 64-pin package. These products differ from the earlier LC66558A Series in the power supply voltage range and certain other electrical characteristics.
Features and Functions
* On-chip ROM and RAM with 6 k (or 8 k) byte and 512 x 4-bit capacities * The same instruction set (with 127 instructions) as the LC66000 Series (except that the SB instruction is not supported) * I/O ports: 54 pins * 8-bit serial interface: two circuits (16-bit cascade connection supported) * Instruction cycle: 0.92 to 10 s (at 3 to 5.5 V) Series Structure
Type No. LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S* LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B LC66562B/566B LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 Note: *: Under development Pin count 42 42 64 42 42 64 42 64 64 42 42 42 42 64 64 ROM capacity 4 k/6 k/8 kB 4 k/6 k/8 kB 6 k/8 k/12 k/16 kB 4 k/6 k/8 kB 4 k/6 k/8 kB 6 k/8 k/12 k/16 kB 4 k/6 k/8 kB 6 k/8 k 12 k/16 kB EPROM 8 kB OTPROM 8 kB EPROM 8 kB OTPROM 8 kB EPROM 16 kB OTPROM 16 kB
* Powerful timers and prescalers 12-bit timer: time-limit timer, event counter, pulse width measurement, square wave output 8-bit timer: time-limit timer, event counter, PWM output, square wave output 12-bit prescaler: time base functions * Powerful 11-factor 8-vector interrupt system External interrupts: 6 factors/3 vectors Internal interrupts: 5 factors/5 vectors * Flexible I/O functions Comparator inputs, three-value inputs, 20 mA drive outputs, 15 V breakdown voltage pins, pull-up/opendrain option switching possible * Runaway detection function (watchdog timer) option * 8-bit I/O function * Power saving functions: halt and hold modes Package: DIP64S, QFP64E * Evaluation LSI: LC66599 (evaluation chip) + EVA850/800-TB665XX LC66E516 (On-chip EPROM microcontrollers) LC66P516 (On-chip OTPROM microcontrollers)
RAM capacity 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W DIP64S DIP42S DIP64S DIP64S DIC42S (window) DIC42S DIC42S (window) DIC42S DIC64S (window) DIC64S DIP42S DIP42S DIP64S DIP42S
Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP64E QFC48 (window) QFP48E QFC48 (window) QFP48E QFC64 (window) QFP64E
Features Normal versions 4.0 to 6.0 V/0.92 s
Low-voltage versions 2.2 to 5.5 V/3.92 s
Low-voltage high-speed versions 3.0 to 5.5 V/0.92 s
Evaluation (window) versions & OTP versions 4.5 to 5.5 V/0.92 s
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
33195TH (OT) No. 5003-1/22
LC66556B, 66558B
Package Dimensions
unit: mm 3071-DIP64S
[LC66556B, 66558B]
unit: mm 3159-QFP64E
[LC66556B, 66558B]
SANYO: DIP64S
SANYO: QIP64E
Pin Assignments
Top view
Top view
We recommend using reflow soldering as the QFP solder mounting technique. Consult your Sanyo representative concerning temperature and other conditions if techniques in which the whole package is to be immersed in a solder dip bath, i.e. solder dip techniques, are to be used.
No. 5003-2/22
LC66556B, 66558B System Block Diagram
Differences between the LC66556B/LC66558B and the LC66508B Series
Item System differences * Hardware wait time (number of cycles) when hold mode is cleared * Value of timer 0 at reset (including the value after hold mode is cleared) LC66508B series (Including the EVA850/800-TB665XX tool) 65536 cycles At 4 MHz (Tcyc = 1 s): about 64 ms The value FF0 is loaded. LC66556B, 66558B 16384 cycles At 4 MHz (Tcyc = 1 s): about 16 ms The value FFC is loaded.
LC66512B, 516B Differences in the major characteristics 4.0 to 6.0 V/0.92 to 10 s * Operating power supply voltage/operating speed LC66E516, P516 4.5 to 5.5 V/0.92 to 10 s
3.0 to 5.5V/0.92 to 10 s
1. An RC oscillator cannot be used with the LC66556B and LC66558B 2. In addition, certain other output current and comparator input voltage specifications differ. For details, see the individual catalogs for the LC66508B, LC66E516 and LC66P516. Keep these differences in mind when using the LC66E516 and LC66P516 evaluation chips.
No. 5003-3/22
LC66556B, 66558B Pin Function Overview
Pin P00 P01 P02 P03 I/O Function I/O ports P00 to P03 * Input or output in 4-bit or 1-bit units * P00 to P03 have control functions in HALT mode. Output drive type Option * Either with pull-up MOS or N-channel OD output * Reset output level Value on reset
I/O
* P-channel: pull-up MOS type * N-channel: small sink current type
High or low (option)
P10 P11 P12 P13
I/O
I/O ports P10 to P13 * Input or output in 4-bit or 1-bit units I/O ports P20 to P23 * Input or output in 4-bit or 1-bit units * P20 is also used as the serial input SI0 pin. P21 is also used as the serial output SO0 pin. P22 is also used as the serial clock SCK0 pin. * P23 is also used as the INT0 interrupt request, as the timer 0 event counter and for pulse width measurement input. I/O ports P30 to P32 * Input or output in 3-bit or 1-bit units * P30 is also used as the INT1 interrupt request. * P31 is also used for square wave output from timer 0. P32 is also used for square wave output from timer 1 and PWM output. Hold mode control input * Hold mode is entered if a HOLD instruction is executed when HOLD is low. * When in hold mode, the CPU is reactivated by setting HOLD to the high level. * P33 can also be used as an input port together with P30 to P32. * When P33/HOLD is low, the CPU will not be reset by a low level on RES. Therefore, RES cannot be used in applications that set P33/HOLD low when power is first applied. I/O ports P40 to P43 * Input or output in 4-bit or 1-bit units * I/O in 8-bit units when used in conjunction with P50 to P53 * Output of 8-bit ROM data when used in conjunction with P50 to P53 I/O ports P50 to P53 * Input or output in 4-bit or 1-bit units * I/O in 8-bit units when used in conjunction with P40 to P43 * Output of 8-bit ROM data when used in conjunction with P40 to P43
* P-channel: pull-up MOS type * N-channel: small sink current type
* Either with pull-up MOS or N-channel OD output * Reset output level
High or low (option)
P20/SI0 P21/SO0 P22/SCK0 P23/INT0
I/O
* P-channel: CMOS type * N-channel: small sink current type * +15 V withstand voltage in Nchannel OD
* Either CMOS or Nchannel OD output
High
P30/INT1 P31/POUT0 P32/POUT1
I/O
* P-channel: CMOS type * N-channel: small sink current type * +15 V withstand voltage in Nchannel OD
* Either CMOS or Nchannel OD output
High
P33/HOLD
I
P40 P41 P42 P43
I/O
* P-channel: pull-up MOS type * N-channel: small sink current type
* Either CMOS or Nchannel OD output
High
P50 P51 P52 P53
I/O
* P-channel: pull-up MOS type * N-channel: small sink current type
* Either CMOS or Nchannel OD output
High
Continued on next page. No. 5003-4/22
LC66556B, 66558B
Continued from preceding page.
Pin I/O Function I/O ports P60 to P63 * Input or output in 4-bit or 1-bit units * P60 is also used as the serial input SI1 pin. * P61 is also used as the serial output SO1 pin. * P62 is also used as the serial clock SCK1 pin. * P63 is also used as the timer 1 event counter input. Output drive type Option Value on reset
P60/SI1 P61/SO1 P62/SCK1 P63/PIN1
I/O
* P-channel: CMOS type * N-channel: small sink current type * +15 V withstand voltage in Nchannel OD
* CMOS or N-channel OD output
High
P70 P71 P72 P73
O
Dedicated output ports P70 to P73 * Output in 4-bit or 1-bit units * The latched output data can be read with input instructions.
* P-channel: pull-up MOS type * N-channel: intermediate sink current type * +15 V withstand voltage in Nchannel OD
* With pull-up MOS transistor or N-channel OD output
High
P80 P81 P82 P83
O
Dedicated output ports P80 to P83 * Output in 4-bit or 1-bit units * The latched output data can be read with input instructions. * A p-channel OD output option is available. I/O ports P90 to P93 * Input or output in 4-bit or 1-bit units * P90 is also used as the INT2 interrupt request. * P91 is also used as the INT3 interrupt request. * P92 is also used as the INT4 interrupt request. * P93 is also used as the INT5 interrupt request. Dedicated output ports PA0 to PA3 * Output in 4-bit or 1-bit units * The latched output data can be read with input instructions.
* P-channel: CMOS type * N-channel: small sink current type
* CMOS or P-channel OD output * The output level at reset
High or low (option)
P90/INT2 P91/INT3 P92/INT4 P93/INT5
I/O
* P-channel: CMOS type * N-channel: small sink current type
* CMOS or N-channel OD output
High
PA0 PA1 PA2 PA3
O
* P-channel: pull-up MOS type * N-channel: intermediate sink current type
* With pull-up MOS or N-channel OD output
High
PB0 PB1 PB2 PB3
O
Dedicated output ports PB0 to PB3 * Output in 4-bit or 1-bit units * The latched output data can be read with input instructions. I/O ports PC0 to PC3 * Input or output in 4-bit or 1-bit units * PC2 is also used as the VREF0 comparator comparison voltage pin. * PC3 is also used as the VREF1 comparator comparison voltage pin. Dedicated input ports PD0 to PD3 * Can be switched to function as comparator inputs under software control. The comparison voltage for PD0 is VREF0. The comparison voltage for PD1 to PD3 is VREF1. Comparison can be specified in units of PD0, PD1, (PD2, PD3).
* P-channel: CMOS type * N-channel: small sink current type
* With pull-up MOS or N-channel OD output
High
PC0 PC1 PC2/VREF0 PC3/VREF1
I/O
* CMOS or N-channel OD output
High
PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3
I
Normal input
Continued on next page. No. 5003-5/22
LC66556B, 66558B
Continued from preceding page.
Pin PE0/TRA PE1/TRB I/O Function Dedicated input port * Can be switched under software control to function as a threevalue input port. System clock oscillator connections When an external clock is used, leave OSC2 open and input the signal to OSC1. System reset input * The CPU is initialized (reset) if a low level is input to RES when P33/HOLD is at the high level. CPU testing This pin must be connected to VSS during normal operation. Power supply connections * Selection of either a ceramic oscillator or external clock input Output drive type Option Value on reset
I
Normal input
OSC1 OSC2
I O
RES
I
TEST
I
VDD VSS
Note: Pull-up MOS output: An output with a pull-up MOS transistor CMOS output: A complementary output OD output: An open drain output
User Option Types 1. Port 0, 1 and 8 reset time output level option The output levels of I/O ports 0, 1 and 8 at reset can be selected from the following two options in 4-bit units.
Option High level output at reset time Low level output at reset time Conditions and notes Ports 0, 1 and/or 8 in 4-bit sets Ports 0, 1 and/or 8 in 4-bit sets
2. Oscillator circuit option
Option Circuit Conditions and notes
External clock
* This input is a Schmitt specification input.
Ceramic oscillator
Note: There is no RC oscillator option.
3. Watchdog timer option The presence or absence of a program runaway detection function (watchdog timer) can be selected as an option.
No. 5003-6/22
LC66556B, 66558B 4. Port output type option * One of the following two output circuit options can be selected for each bit in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P7, P9, PA, PB and PC.
Option Circuit Conditions and notes
Open drain output
P7, PA and PB are output only pins. P2, P3, P6 and P9 are Schmitt inputs.
P7, PA and PB are output only pins. P2, P3, P6 and P9 are Schmitt inputs. Built-in pull-up resistor output CMOS outputs (P2, P3, P6, P9 and PC) and pull-up MOS outputs (P0, P1, P4, P5, P7, PA and PB) are differentiated.
* The P8 circuits can be selected from the following two options in bit units.
Option Circuit Conditions and notes
Open drain output
Built-in pull-up resistor output
* The PD comparator inputs and the PE three-value inputs are selected in software.
No. 5003-7/22
LC66556B, 66558B
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN (1) VIN (2) VOUT (1) VOUT (2) ION (1) Output current per pin ION (2) -IOP (1) -IOP (2) ION (1) Total pin current ION (2) -IOP (1) -IOP (2) Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD P2, P3 (except for the P33/HOLD pin) and P6 Other inputs P2, P3 (except for the P33/HOLD pin), P6, P7 and PA Other outputs P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P8, P9 and PC P7, PA, PB P0, P1, P4, P5, P7, PA, PB P2, P3 (except for the P33/HOLD pin), P6, P8, P9 and PC P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P7 and P8 P0, P1, P9, PA, PB, PC P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P7 and P8 P0, P1, P9, PA, PB, PC Ta = -30 to +70C: DIP64S (QIP64E) Conditions Ratings -0.3 to +7.0 -0.3 to +15.0 -0.3 to VDD + 0.3 -0.3 to +15.0 -0.3 to VDD + 0.3 4 20 2 4 75 75 25 25 600 (430) -30 to +70 -55 to +125 Unit V V V V V mA mA mA mA mA mA mA mA mW C C 1 2 1 2 3 3 4 4 3 3 4 4 5 Note
Output voltage
Note: 1. Applies to open drain output specification pins. The rating from the "other pin" entry applies for specifications other than the open drain output specification. 2. Levels up to the free-running oscillation level are allowed for the oscillator input and output pins. 3. Inflow current (For P8, the CMOS output specifications apply.) 4. Outflow current (Applies to pull-up output specification and CMOS output specification pins except P8.) 5. We recommend using reflow soldering methods to mount the QFP package version. Contact your Sanyo sales representative to discuss process conditions if techniques in which the whole package is immersed in a solder bath (solder dip or spray techniques) are used.
Allowable Operating Ranges at Ta = -30 to + 70C, VSS = 0 V, VDD = 3.0 to 5.5 V unless specified otherwise
Parameter Operating supply voltage Memory retention supply voltage Symbol VDD VDD (H) VIH (1) VIH (2) Input high level Voltage VIH (3) VIH (4) Intermediate level input voltage VIM VCMM (1) Common-mode input voltage range VCMM (2) VIL (1) VIL (2) Low level input voltage VIL (3) VIL (4) Operating frequency (instruction cycle time) fop (TCYC) VDD VDD: In hold mode P2, P3 (except for the P33/HOLD pin), P6: With the output n-channel transistor off P33/HOLD, P9, RES, OSC1: With the output n-channel transistor off P0, P1, P4, P5, PC, PD, PE: With the output n-channel transistor off PE: When three-state input is used PE: When three-state input is used PD0, PC2: When comparator input is used PD1, PD2, PD3, PC3: When comparator input is used P2, P3 (except for the P33/HOLD pin), P6, P9, RES, OSC1:N-channel output, transistor off P33/HOLD: VDD = 1.8 to 5.5 V P0, P1, P4, P5, PC, PD, PE, TEST: N-channel output, transistor off PE: When three-state input is used Conditions min 3.0 1.8 0.8 VDD 0.8 VDD 0.75 VDD 0.8 VDD 0.4 VDD 1.5 VSS VSS VSS VSS VSS 0.4 (10) typ max 5.5 5.5 13.5 VDD VDD VDD 0.6 VDD VDD VDD - 1.5 0.2 VDD 0.2 VDD 0.25 VDD 0.2 VDD 4.35 (0.92) Unit V V V V V V V V V V V V V MHz (s) 3 2 1 2 3 Note
Note: 1. Applies to open drain specification pins. However, the rating for VIH (2) applies to the P33/HOLD pin. Ports P2, P3 and P6 cannot be used as input pins when CMOS output specifications are used. 2. Applies to open drain specification pins. P9, which has CMOS output specifications, can be used as input pins. 3. When PE is used as a three-value input, VIH (4), VIM and VIL (4) apply. Port PC cannot be used as input pins when CMOS output specifications are used.
Continued on next page. No. 5003-8/22
LC66556B, 66558B
Continued from preceding page.
Parameter [External clock input conditions] Frequency fext OSC1: See Figure 1. With the signal input to OSC1 and with OSC2 open (with external clock input selected for the oscillator circuit option) OSC1: See Figure 1. With the signal input to OSC1 and with OSC2 open (with external clock input selected for the oscillator circuit option) 0.4 4.35 MHz Symbol Conditions min typ max Unit Note
Pulse width
textH, textL
100
ns
Rise and fall times
OSC1: See Figure 1. With the signal input to OSC1 textR, textF and with OSC2 open (with external clock input selected for the oscillator circuit option)
30
ns
Electrical Characteristics at Ta = -30 to + 70C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified
Parameter Symbol IIH (1) Input high level current IIH (2) Conditions P2, P3 (except for the P33/HOLD pin), P6: VIN = 13.5 V, N-channel output, transistor off P0, P1, P4, P5, P9, PC, OSC1, RES, P33/HOLD (except for PD, PE, PC2 and PC3): VIN = VDD, N-channel output, transistor off PD, PE, PC2, PC3: VIN = VDD, N-channel output, transistor off Inputs other than PD, PE, PC2, PC3: VIN = VSS, N-channel output, transistor off PC2, PC3, PD, PE: VIN = VSS, N-channel output, transistor off P2, P3 (except for the P33/HOLD pin), P6, P8, P9, PC: IOH = -1 mA P2, P3 (except for the P33/HOLD pin), P6, P8, P9, PC: IOH = -0.1 mA P0, P1, P4, P5, P7, PA, PB: IOH = -50 A VOH (2) P0, P1, P4, P5, P7, PA, PB: IOH = -30 A P0, P1, P4, P5, P7, PA, PB: VIN = VSS, VDD = 5.5 V P0, P1, P2, P3, P4, P5, P6, P8, P9, PC (except for the P33/HOLD pin): IOL = 1.6 mA P7, PA, PB: IOL = 8 mA P2, P3, P6, P7, PA: VIN = 13.5 V (except for P2, P3, P6, P7, P8 and PA): VIN = VDD P8: VIN = VSS PD1, PD2, PD3: VIN = VSS to VDD - 1.5 V PD0: VIN = 1.5 V to VDD -1.0 50 50 300 300 -1.0 -1.0 VDD - 1.0 VDD - 0.5 VDD - 1.0 VDD - 0.5 -1.6 0.4 1.5 5.0 1.0 min typ max 5.0 Unit A Note 1
1.0
A
1
IIH (3) IIL (1) Input low level current IIL (2)
1.0
A A A
1 2 2
VOH (1) Output high level voltage
V
3
V
4
Output pull-up current
IPO VOL (1) VOL (2) IOFF (1)
mA V V A A A mV mV
4 5
Output low level voltage
6 6 7
Output off leakage current
IOFF (2) IOFF (3) VOFF (1) VOFF (2)
Comparator offset voltage [Schmitt characteristics] Hysteresis voltage High level threshold voltage Low level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time
VHIS Vt H Vt L P2, P3, RES, P6, P9, OSC1, (RC, EXT) 0.5 VDD 0.2 VDD OSC1, OSC2: See Figure 2, 4 MHz See Figure 3, 4 MHz
0.1 VDD 0.8 VDD 0.5 VDD 4.0 10
V V V
fCF tCFS
MHz ms
Note: 1. Common input and output ports with open-drain output specifications are specified for the state with the output N-channel transistor turned off. These pins cannot be used for input when the CMOS output specification option is selected. 2. Common input and output ports with open-drain output specifications are specified for the state with the output N-channel transistor turned off. Ratings for pull-up output specification pins are stipulated for the output pull-up current IPO. These pins cannot be used for input when the CMOS output specification option is selected. 3. Stipulated for CMOS output specifications with the output N-channel transistor in the off state. (This also applies to P8 when P-channel open drain is selected.) 4. Stipulated for pull-up output specifications with the output N-channel transistor in the off state. 5. Stipulated for P8 with CMOS output specifications. 6. Stipulated for open drain output specifications with the output N-channel transistor in the off state. 7. Stipulated for open drain output specifications with the output P-channel transistor in the off state.
Continued on next page. No. 5003-9/22
LC66556B, 66558B
Continued from preceding page.
Parameter [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF tICK tCKI S10, SI1, SI0, SI1: With the timing in Figure 4. Stipulated with respect to the rising edge for SCK0 and SCK1. 0.3 0.3 SCK0, SCK1: With the timing from Figure 4 and the test load from Figure 5 0.9 2.0 0.4 1.0 0.1 s TCYC s TCYC s Symbol Conditions min typ max Unit Note
Input Low level/high level pulse widths Output Rise/fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time [Pulse input conditions] INT0 High and low level pulse widths
High and low level pulse widths for interrupt inputs other than INT0
Output
s s
tCKO
SO0, SO1: With the timing from Figure 5 and the test load from Figure 5. Stipulated with respect to the falling edge for SCK0 and SCK1.
0.3
s
tI0H, tI0L
INT0, See Figure 6: Conditions such that the INT0 interrupt is accepted Conditions such that timer 0 event counter and pulse width measurement inputs are accepted INT1, INT2, INT3, INT4, INT5, See Figure 6: Conditions such that all interrupts are accepted PIN1, See Figure 6: Conditions such that timer 1 event counter inputs are accepted RES, See Figure 6: Conditions such that reset can occur PD, See Figure 7 VDD: 4 MHz ceramic oscillator VDD: 4 MHz external clock VDD: 4 MHz ceramic oscillator VDD: 4 MHz external clock VDD: VDD = 1.8 to 5.5 V
2
TCYC
tI1H, tI1L tPINH, tPINL tRSH, tRSL TRS IDD op IDDHALT IDDHOLD
2 2 3 20 3.0 3.0 1.0 1.0 0.01 5.0 5.0 2.0 2.0 10
TCYC TCYC TCYC ms mA mA mA mA A 8
PIN1 High and low level pulse widths RES High and low level pulse widths Comparator response speed Operating mode current drain
HALT mode current drain Hold mode current drain Note: 8. Reset state
Figure 1 External Clock Input Waveform
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
No. 5003-10/22
LC66556B, 66558B Table 1 Ceramic Oscillator Guaranteed Constants
C1 = 33 pF 10% 4 MHz (Murata Mfg. Co., Ltd.) C1 = 33 pF 10% CSA4.00MG Rd = 0 4 MHz (Murata Mfg. Co., Ltd.) CST4.00MG C1 = 33 pF 10% 4 MHz (Kyocera Corporation) C1 = 33 pF 10% KBR4.0 MS Rd = 0 4 MHz (Kyocera Corporation) KBR4.0MES
External capacitance
Internal capacitance
Figure 4 Serial I/O Timing
Figure 5 Timing Load
Figure 6 Input Timing for INT0, INT1, INT2, INT3, INT4, INT5, PIN1 and RES
Figure 7 Comparator Response Speed Trs Timing
No. 5003-11/22
LC66556B, 66558B Application Development Tools Programs for the LC66556B and LC66558B microprocessors are developed on an IBM-PC compatible personal computer running the MS-DOS operating system. A cross assembler and other tools are available. To make application development more convenient, Sanyo also provides a program debugging unit (EVA850/800), an evaluation board (EVA850/800-TB665XX), an evaluation chip (LC66599) and an on-chip EPROM microprocessor (LC66E516).
Structure of the Application Development Tools 1. Program debugging unit (EVA850/800) This is an emulator that provides functions for EPROM writing and serial data communications with external equipment (such as a host computer). It supports application development in machine language and program modification. Its main debugging functions include breaking, stepping and tracing. (The MPM665XX is used for the EVA850/800 monitor ROM.) 2. Evaluation chip board (EVA800/850-TB665XX) The evaluation chip signals and ports are output to the 64-pin connector and when the output cable is connected, the evaluation chip board converts these signals to the same pin assignments as those on the mass production chip. The evaluation chip board includes jumpers for setting options and other states and these jumper settings allow the evaluation chip to implement the same I/O circuit types and functions as the mass production chip. However, there are differences in the hold mode clear timing and the electrical characteristics. Jumpers
Type Jumper EXT Jumper setting and mode RC CF RC oscillator CF oscillator OSC Jumper 1 (J1) External oscillator (external clock) INT (a) Reset method Jumper 2 (J2:RES) Reset by a RUN instruction from the host computer. ON (a) Power supply to the user application board Jumper 3 (J3:VDD) VDD is supplied to the user application printed circuit board through the evaluation chip board.
Reset by the reset circuit on EXT (b) the user application printed circuit board.
Separate power supplies on the user OFF (b) application printed circuit board and the evaluation chip board
Switches (SW1)
Type Switch Switch setting and mode ON OFF P0S Port 0 high Port 0 low ON OFF Port 0, 1 and 8 output levels on reset P1S Port 1 high Port 1 low ON OFF P8S Port 8 high Port 8 low ON OFF Watchdog timer presence or absence setting WDC Watchdog timer present Watchdog timer absent
Note: Switches RC0 and RC1 must both be set to the on position.
No. 5003-12/22
LC66556B, 66558B Switches SW2 to SW14: Pull-up resistor option settings 1. Set the corresponding switch to the on position for built-in pull-up resistors and set the switch to the off position for open drain output. (SW10 is used for the port 8 pull-down resistor setting.) 2. These settings can be specified for individual pins. 3. Cross assembler
Cross assembler (file name) Object microprocessors LC66562B/566B (LC66E516/P516) (LC66599) Limitations on program creation SB instruction limitations * LC66556B: SB0, SB1, SB2 and SB3 cannot be used * LC66558B: SB0, SB1, SB2 and SB3 cannot be used * LC66E516/P516: SB0, SB1, SB2 and SB3 can be used * LC66599: SB0, SB1, SB2 and SB3 can be used
LC66S. EXE
4. Simulation chip (See the LC66E516 individual product catalog for more details.) The LC66E516 simulation chip is an on-chip EPROM microprocessor. Mounted configuration operation can be confirmed in the application product by using a dedicated conversion board (the W66E516DH for DIC products and the W66E516QH for QFP products) and writing programs with a commercial PROM writer. * Form The LC66E516 has a pin assignment and functions identical to those of the LC66556B and LC66558B. However, there are differences in the hold mode clear timing and the electrical characteristics. The figure below shows the pin assignment . The figure below shows the pin assignment . * Options The options (the port 0, 1 and 8 levels at reset, the watchdog timer and the port output circuit types) for the microprocessor to be evaluated can be specified by EPROM data. This allows evaluation with the same peripheral circuits as those that will be used in the mass production product. Pin Assignments
Top view
Top view
No. 5003-13/22
LC66556B, 66558B LC665XX Series Instruction Table (by function) Abbreviations: AC: Accumulator E: E register CF: Carry flag ZF: Zero flag HL: Data pointer DPH, DPL XY: Data pointer DPX, DPY M: Data memory M (HL): Data memory pointed to by the DPH, DPL data pointer M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer SP: Stack pointer M2 (SP): Two words of data memory pointed to by the stack pointer M4 (SP): Four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: Bit specification
t2 Bit 11 23 10 22 01 21 00 20
PCh: PCm: PCl: Fn: TIMER0: TIMER1: SIO: P: P (i4): INT: ( ), [ ]: : : : : +: -: --:
Bits 8 to 11 in the PC Bits 4 to 7 in the PC Bits 0 to 3 in the PC User flag, n = 0 to 15 Timer 0 Timer 1 Serial register Port Port indicated by 4 bits of immediate data Interrupt enable flag Indicates the contents of a location Transfer direction, result Exclusive or Logical and Logical or Addition Subtraction Taking the one's complement
No. 5003-14/22
LC66556B, 66558B
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Accumulator manipulation instructions] CLA DAA Clear AC Decimal adjust AC in addition Decimal adjust AC in subtraction Clear CF Set CF Complement AC Increment AC Decrement AC Rotate AC right through CF Rotate AC left through CF Transfer AC to E Transfer E to AC Exchange AC with E 1000 1100 0010 1100 0010 0001 0001 0001 0001 0010 0001 0000 1111 0110 1111 1010 1110 1111 1000 0100 0100 0000 1 2 1 2 AC 0 Clear AC. (Equivalent to LAI 0.) AC (AC) + 6 Add six to AC. (Equivalent to ADI 6.) AC (AC) + 10 (Equivalent to ADI 0AH.) CF 0 CF 1 AC (AC) AC (AC) + 1 AC (AC) - 1 AC3 (CF), ACn (ACn + 1), CF (AC0) AC0 (CF), ACn + 1 (ACn), CF (AC3) E (AC) AC (E) (AC) (E) Add 10 to AC. Clear CF to 0. Set CF to 1. Take the one's complement of AC. Increment AC. Decrement AC. Shift AC (including CF) right. ZF ZF Has a vertical skip function.
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
DAS CLC STC CMA IA DA RAR
2 1 1 1 1 1 1
2 1 1 1 1 1 1
ZF CF CF ZF ZF, CF ZF, CF CF
RAL TAE TEA XAE
0000 0100 0100 0100
0001 0101 0110 0100
1 1 1 1
1 1 1 1
Shift AC (including CF) left. Move the contents of AC to E.
CF, ZF
Move the contents of E to AC. ZF Exchange the contents of AC and E.
[Memory manipulation instructions] IM DM IMDR i8 Increment M Decrement M Increment M direct 0001 0010 1100 I7 I6 I5 I4 1100 I7 I6 I5 I4 0000 0010 0010 0010 0111 I3 I2 I1 I0 0011 I3 I2 I1 I0 1 1 t1 t0 1 1 t1 t0 1 1 2 2 1 1 1 1 2 2 1 1 M (HL) [M (HL)] + 1 M (HL) [M (HL)] - 1 M (i8) [M (i8)] + 1 M (i8) [M (i8)] - 1 [M (HL), t2] 1 [M (HL), t2] 0 Increment M (HL). Decrement M (HL). Increment M (i8). Decrement M (i8). Set the bit in M (HL) specified by t0 and t1 to 1. Clear the bit in M (HL) specified by t0 and t1 to 0. ZF ZF, CF ZF, CF ZF, CF ZF, CF
DMDR i8 Decrement M direct SMB t2 RMB t2 Set M data bit Reset M data bit
[Arithmetic, logic and comparison instructions] AC (AC) + [M (HL)] Add the contents of AC and M (HL) as two's complement values and store the result in AC.
AD
Add M to AC
0000
0110
1
1
ZF, CF
ADDR i8 Add M direct to AC
1100 I7 I6 I5 I4
1001 I3 I2 I1 I0
2
2
Add the contents of AC and M (i8) as two's complement AC (AC) + [M (i8)] values and store the result in AC. AC (AC) + [M (HL)] + (CF) Add the contents of AC, M (HL) and CF as two's complement values and store the result in AC. Add the contents of AC and the immediate data as two's complement values and store the result in AC. Subtract the contents of AC and CF from M (HL) as two's complement values and store the result in AC. Take the logical and of AC and M (HL) and store the result in AC. Take the logical or of AC and M (HL) and store the result in AC.
ZF, CF
ADC
Add M to AC with CF 0 0 0 0
0010
1
1
ZF, CF
ADI i4
Add immediate data to AC
1100 0010
1111 I3 I2 I1 I0
2
2
AC (AC) + I3, I2, I1, I0
ZF
SUBC
Subtract AC from M with CF
0001
0111
1
1
AC [M (HL)] - (AC) - (CF) AC (AC) [M (HL)] AC (AC) [M (HL)]
ZF, CF
CF will be zero if there was a borrow and one otherwise.
ANDA
And M with AC then store AC Or M with AC then store AC
0000
0111
1
1
ZF
ORA
0000
0101
1
1
ZF
Continued on next page. No. 5003-15/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Arithmetic, logic and comparison instructions] EXL Exclusive or M with AC then store AC And M with AC then store M Or M with AC then store M 0001 0101 1 1 AC (AC) [M (HL)] M (HL) (AC) [M (HL)] M (HL) (AC) [M (HL)] Take the logical exclusive or of AC and M (HL) and store the result in AC. Take the logical and of AC and M (HL) and store the result in M (HL). Take the logical or of AC and M (HL) and store the result in M (HL). Compare the contents of AC and M (HL) and set or clear CF and ZF according to the result. CM Compare AC with M 0001 0110 1 1 [M (HL)] + (AC) + 1 Magnitude comparison [M (HL)] > (AC) [M (HL)] = (AC) [M (HL)] < (AC) CF ZF 0 1 1 0 1 0 ZF, CF ZF
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
ANDM
0000
0011
1
1
ZF
ORM
0000
0100
1
1
ZF
Compare the contents of AC and the immediate data I3 I2 I1 I0 and set or clear CF and ZF according to the result. CI i4 Compare AC with immediate data 1100 1010 1111 I3 I2 I1 I0 2 2 I3 I2 I1 I0 + (AC) + 1 Magnitude comparison I3 I2 I1 I0 > AC I3 I2 I1 I0 = AC I3 I2 I1 I0 < AC ZF 1 if (DPL) = I3 I2 I1 I0 ZF 0 if (DPL) I3 I2 I1 I0 ZF 1 if (AC, t2) = [M (HL), t2] ZF 0 if (AC, t2) [M (HL), t2] AC M (HL), E M (HL + 1) AC I3 I2 I1 I0 AC [M (i8)] M (HL) (AC) M (HL) (AC) M (HL + 1) (E) CF ZF 0 1 1 0 1 0 ZF, CF
CLI i4
Compare DPL with immediate data
1100 1011
1111 I3 I2 I1 I0
2
2
Compare the contents of DPL with the immediate data. Set ZF if identical and clear ZF if not. Compare the corresponding bits specified by t0 and t1 in AC and M (HL). Set ZF if identical and clear ZF if not.
ZF
CMB t2
Compare AC bit with M data bit
1100 1101
1111 0 0 t1 t0
2
2
ZF
[Load and store instructions] LAE LAI i4 LADR i8 S SAE Load AC and E from M2 (HL) Load AC with immediate data Load AC from M direct Store AC to M Store AC and E to M2 (HL) 0101 1000 1100 I7 I6 I5 I4 0100 0101 1100 I3 I2 I1 I0 0001 I3 I2 I1 I0 0111 1110 1 1 2 1 1 1 1 2 1 1 Load the contents of M2 (HL) into AC, E. Load the immediate data into AC. Load the contents of M (i8) into AC. Store the contents of AC into M (HL). Store the contents of AC, E into M2 (HL). Load the contents of M (reg) into AC. The reg is either HL or XY depending on t0. reg HL XY t0 0 1 ZF ZF Has a vertical skip function
LA reg
Load AC from M (reg)
0100
1 0 t0 0
1
1
AC [M (reg)]
ZF
Continued on next page. No. 5003-16/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Load and store instructions] Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. Exchange the contents of M (reg) and AC. The reg is either HL or XY depending on t0. reg HL XY t0 0 1 ZF is set according to the result of incrementing DPL or DPY.
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
LA reg, I
Load AC from M (reg) 0100 then increment reg
1 0 t0 1
1
2
AC [M (reg)] DPL (DPL) + 1 or DPY (DPY) + 1
Load AC from M (reg) LA reg, D 0101 then decrement reg
1 0 t0 1
1
2
AC [M (reg)] DPL (DPL) - 1 or DPY (DPY) - 1
ZF is set according to the result of decrementing DPL or DPY.
XA reg
Exchange AC with M (reg)
0100
1 1 t0 0
1
1
(AC) [M (reg)]
Exchange AC with XA reg, I M (reg) then increment reg
0100
1 1 t0 1
1
2
(AC) [M (reg)] DPL (DPL) + 1 or DPY (DPY) + 1
Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. The relationship between t0 and reg is the as that for the XA reg instruction. Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. The relationship between t0 and reg is the as that for the XA reg instruction. Exchange the contents of AC and M (i8). Load the immediate data i8 into E, AC. Load into E, AC the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. Output from ports 4 and 5 the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC.
ZF
ZF is set according to the result of incrementing DPL or DPY.
Exchange AC with XA reg, D M (reg) then decrement reg
0101
1 1 t0 1
1
2
(AC) [M (reg)] DPL (DPL) - 1 or DPY (DPY) - 1
ZF
ZF is set according to the result of decrementing DPL or DPY.
XADR i8 LEAI i8
Exchange AC with M direct Load E & AC with immediate data
1100 I7 I6 I5 I4 1100 I7 I6 I5 I4
1000 I3 I2 I1 I0 0110 I3 I2 I1 I0
2 2
2 2
(AC) [M (i8)] E I7 I6 I5 I4 AC I3 I2 I1 I0 E, AC [ROM (PCh, E, AC)]
RTBL
Read table data from 0101 program ROM
1010
1
2
RTBLP
Read table data from program ROM then 0101 output to P4, 5
1000
1
2
Port 4, 5 [ROM (PCh, E, AC)]
[Data pointer manipulation instructions] Load DPH with zero and DPL with immediate data respectively Load DPH with immediate data Load DPL with immediate data Load DPH, DPL with immediate data Load DPX, DPY with immediate data DPH 0 DPL I3 I2 I1 I0 DPH I3 I2 I1 I0 DPL I3 I2 I1 I0 DPH I7 I6 I5 I4 DPL I3 I2 I1 I0 DPX I7 I6 I5 I4 DPY I3 I2 I1 I0 Load zero into DPH and the immediate data i4 into DPL. Load the immediate data i4 into DPH. Load the immediate data i4 into DPL. Load the immediate data into DLH, DPL. Load the immediate data into DLX, DPY.
LDZ i4
0110
I3 I2 I1 I0 1111 I3 I2 I1 I0 1111 I3 I2 I1 I0 0000 I3 I2 I1 I0 0010 I3 I2 I1 I0
1
1
LHI i4 LLI i4 LHLI i8 LXYI i8
1100 0000 1100 0001 1100 I7 I6 I5 I4 1100 I7 I6 I5 I4
2 2 2 2
2 2 2 2
Continued on next page. No. 5003-17/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Data pointer manipulation instructions] IL DL IY DY TAH THA XAH TAL TLA XAL TAX TXA XAX TAY TYA XAY Increment DPL Decrement DPL Increment DPY Decrement DPY Transfer AC to DPH Transfer DPH to AC Exchange AC with DPH Transfer AC to DPL Transfer DPL to AC Exchange AC with DPL Transfer AC to DPX Transfer DPX to AC Exchange AC with DPX Transfer AC to DPY Transfer DPY to AC Exchange AC with DPY 0001 0010 0001 0010 1100 1111 1100 1110 0100 1100 1111 1100 1110 0100 1100 1111 1100 1110 0100 1100 1111 1100 1110 0100 0001 0001 0011 0011 1111 0000 1111 0000 0000 1111 0001 1111 0001 0001 1111 0010 1111 0010 0010 1111 0011 1111 0011 0011 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1 DPL (DPL) + 1 DPL (DPL) - 1 DPY (DPY) + 1 DPY (DPY) - 1 DPH (AC) AC (DPH) (AC) (DPH) DPL (AC) AC (DPL) (AC) (DPL) DPX (AC) AC (DPX) (AC) (DPX) DPY (AC) AC (DPY) (AC) (DPY) Increment the contents of DPL. Decrement the contents of DPL. Increment the contents of DPY. Decrement the contents of DPY. Transfer the contents of AC to DPH. Transfer the contents of DPH to AC. Exchange the contents of AC and DPH. Transfer the contents of AC to DPL. Transfer the contents of DPL to AC. Exchange the contents of AC and DPL. Transfer the contents of AC to DPX. Transfer the contents of DPX to AC. Exchange the contents of AC and DPX. Transfer the contents of AC to DPY. Transfer the contents of DPY to AC. Exchange the contents of AC and DPY. Set the flag specified by n4 to 1. Reset the flag specified by n4 to 0. ZF ZF ZF ZF ZF ZF ZF ZF ZF
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
[Flag manipulation instructions] SFB n4 RFB n4 Set flag bit Reset flag bit 0111 0011 n3 n2 n1 n0 n3 n2 n1 n0 1 1 1 1 Fn 1 Fn 0
[Jump and subroutine instructions] PC13, 12 PC13, 12 PC11 to 0 P11 to P0 PC13 to 8 PC13 to 8, PC7 to 4 (E), PC3 to 0 (AC) PC13 to 11 0, PC10 to 0 P10 to P0, M4 (SP) (CF, ZF, PC13 to 0), SP (SP)-4 Jump to the location in the same bank specified by the immediate data P12. Jump to the location determined by replacing the lower 8 bits of the PC by E, AC. This becomes PC12 + (PC12) immediately following a BANK instruction.
JMP addr
Jump in the current bank
1 1 1 0 P11P10P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
2
2
JPEA
Jump to the address stored at E and AC in the current page
0010
0111
1
1
CAL addr
Call subroutine
0 1 0 1 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
2
2
Call a subroutine.
CZP addr
Call subroutine in the 1010 zero page
P3 P2 P1 P0
1
2
PC13 to 6, PC10 0, PC5 to 2 P3 to P0, Call a subroutine on page 0 M4 (SP) in bank 0. (CF, ZF, PC12 to 0), SP SP-4 Change the memory bank and register bank.
BANK
Change bank
0001
1011
1
1
Continued on next page. No. 5003-18/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Jump and subroutine instructions] Store the contents of reg in M2 (SP). Subtract 2 from SP after the store. PUSH reg Push reg on M2 (SP) 1100 1111 1111 1 i1 i0 0 2 2 M2 (SP) (reg) SP (SP)-2 reg HL XY AE Illegal i1 0 0 1 1 i0 0 1 0 1
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
POP reg
Pop reg off M2 (SP)
1100 1110
1111 1 i1 i0 0
2
2
SP (SP) + 2 reg [M2 (SP)]
Add 2 to SP and then load the contents of M2(SP) into reg. The relation between i1i0 and reg is the same as that for the PUSH reg instruction. Return from a subroutine or interrupt handling routine. ZF and CF are not restored. Return from a subroutine or interrupt handling routine. ZF and CF are restored. ZF, CF
RT
Return from subroutine Return from interrupt routine
0001
1100
1
2
SP (SP) + 4 PC [M4 (SP)] SP (SP) + 4 PC [M4 (SP)] CF, ZF [M4 (SP)] PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =0
RTI
0001
1101
1
2
[Branch instructions] BAt2 addr 1 1 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is 1. Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is 0. Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is 1. Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is 0. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out.
Branch on AC bit
2
2
BNAt2 addr
Branch on no AC bit
1 0 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BMt2 addr
Branch on M bit
1 1 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BNMt2 addr
Branch on no M bit
1 0 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BPt2 addr
Branch on Port bit
1 1 0 1 1 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =1
Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is 1.
BNPt2 addr
1 0 0 1 1 0 t1 t0 Branch on no Port bit P7 P6 P5 P4 P3 P2 P1 P0
2
2
PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =0
Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is 0.
Continued on next page. No. 5003-19/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Branch instructions] 1101 1100 P7 P6 P5 P4 P3 P2 P1 P0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 0 Branch to the location in the same page specified by P7 to P0 if CF is 1 Branch to the location in the same page specified by P7 to P0 if CF is 0. Branch to the location in the same page specified by P7 to P0 if ZF is 1. Branch to the location in the same page specified by P7 to P0 if ZF is 0. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is 1. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is 0.
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
BC addr
Branch on CF
2
2
BNC addr
Branch on no CF
1001 1100 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BZ addr
Branch on ZF
1101 1101 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BNZ addr
Branch on no ZF
1001 1101 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BFn4 addr
Branch on flag bit
1 1 1 1 n3 n 2 n 1 n 0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BNFn4 addr
Branch on no flag bit
1 0 1 1 n3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
[I/O instructions] IP0 IP IPM IPDR i4 Input port 0 to AC Input port to AC Input port to M Input port to AC direct Input port 4, 5 to E, AC respectively Output AC to port Output M to port Output AC to port direct Output E, AC to port 4, 5 respectively 0010 0010 0001 1100 0110 1100 1101 0010 0001 1100 0111 1100 1101 0000 0110 1001 1111 I3 I2 I1 I0 1111 0100 0101 1010 1111 I3 I2 I1 I0 1111 0101 1 1 1 2 1 1 1 2 AC (P0) AC [P (DPL)] M (HL) [P (DPL)] AC [P (i4)] E [P (4)] AC [P (5)] P (DPL) (AC) P (DPL) [M (HL)] P (i4) (AC) P (4) (E) P (5) (AC) [P (DPL), t2] 1 Input the contents of port 0 to AC. Input the contents of port P (DPL) to AC. Input the contents of port P (DPL) to M (HL). Input the contents of P (i4) to AC. Input the contents of ports P (4) and P (5) to E and AC respectively. Output the contents of AC to port P (DPL). Output the contents of M (HL) to port P (DPL). Output the contents of AC to P (i4). Output the contents of E and AC to ports P (4) and P (5) respectively. Set to one the bit in port P (DPL) specified by the immediate data t1 t0. Clear to zero the bit in port P (DPL) specified by the immediate data t1 t0. ZF ZF ZF ZF
IP45
2
2
OP OPM OPDR i4
1 1 2
1 1 2
OP45
2
2
SPB t2
Set port bit
0000
1 0 t1 t0
1
1
RPB t2
Reset port bit
0010
1 0 t1 t0
1
1
[P (DPL), t2] 0 P (P3 to P0) [P (P3 to P0)] I3 to I0 P (P3 to P0) [P (P3 to P0)] I3 to I0
And port with ANDPDR immediate data then i4, p4 output Or port with immediate data then output
1100 0101 I3 I2 I1 I0 P3 P2 P1 P0
2
2
Take the logical and of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). Take the logical or of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0).
ORPDR i4, p4
1100 0100 I3 I2 I1 I0 P3 P2 P1 P0
2
2
Continued on next page. No. 5003-20/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Timer control instructions] WTTM0 Write timer 0 1100 1010 1 2 Write the contents of M2 (HL), TIMER0 [M2 (HL)], AC into the timer 0 reload (AC) register. TIMER1 (E), (AC) Write the contents of E, AC into the timer 1 reload register A. Read out the contents of the timer 0 counter into M2 (HL), AC. Read out the contents of the timer 1 counter into E, AC. Start the timer 0 counter. Start the timer 1 counter. Stop the timer 0 counter. Stop the timer 1 counter.
Number of bytes Number of cycles
Operation
Description
Affected status bits
Note
WTTM1
Write timer 1
1100 1111
1111 0100
2
2
RTIM0
Read timer 0
1100 1100 1111 1100 1110 1100 1110 1100 1111 1100 1111
1011 1111 0101 1111 0110 1111 0111 1111 0110 1111 0111
1
2
M2 (HL), AC (TIMER0) E, AC (TIMER1) Start timer 0 counter Start timer 1 counter Stop timer 0 counter Stop timer 1 counter
RTIM1
Read timer 1
2 2 2 2 2
2 2 2 2 2
START0 Start timer 0 START1 Start timer 1 STOP0 STOP1 Stop timer 0 Stop timer 1
[Interrupt control instructions] MSET MRESET EIH i4 EiL i4 DIH i4 DIL i4 WTSP RSP Set interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt low Disable interrupt high Disable interrupt low Write SP Read SP 1100 0101 1100 1001 1100 0101 1100 0100 1100 1001 1100 1000 1100 1101 1100 1101 1101 0000 1101 0000 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1111 1010 1111 1011 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MSE 1 MSE 0 EDIH (EDIH) EDIL (EDIL) EDIH (EDIH) EDIL (EDIL) SP (E), (AC) E, AC (SP) i4 i4 i4 i4 Set the interrupt master enable flag to 1. Clear the interrupt master enable flag to 0. Set the interrupt enable flag to 1. Set the interrupt enable flag to 1. Clear the interrupt enable flag to 0. Clear the interrupt enable flag to 0. Transfer the contents of E, AC to SP. Transfer the contents of SP to E, AC. ZF ZF
[Standby control instructions] HALT HOLD HALT HOLD 1100 1101 1100 1101 1111 1110 1111 1111 2 2 2 2 HALT HOLD Enter halt mode. Enter hold mode.
[Serial I/O control instructions] STARTS Start serial I O WTSIO RSIO Write serial I O Read serial I O 1100 1110 1100 1110 1100 1111 1111 1110 1111 1111 1111 1111 2 2 2 2 2 2 START SI O SIO (E), (AC) E, AC (SIO) Start SIO operation. Write the contents of E, AC to SIO. Read the contents of SIO into E, AC.
[Other instructions] NOP No operation 0000 1100 SB i2 Select bank 1100 0000 1111 0 0 I1 I0 2 2 1 1 No operation Consume one machine cycle without performing any operation. Specify the memory bank. Illegal instruction
PC13, PC12 I1 I0
No. 5003-21/22
LC66556B, 66558B
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1995. Specifications and information herein are subject to change without notice. PS No. 5003-22/22

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